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Verilog hardware description language
URI:
https://gptkb.org/entity/Verilog_hardware_description_language
GPTKB entity
Statements (52)
Predicate
Object
gptkbp:instanceOf
hardware description language
gptkbp:abbreviation
gptkb:Verilog
gptkbp:acquiredBy
gptkb:Cadence_Design_Systems
gptkbp:category
digital electronics
hardware description languages
electronic design automation
gptkbp:competitor
gptkb:VHDL
gptkbp:designedFor
modeling electronic systems
gptkbp:developedBy
gptkb:Gateway_Design_Automation
gptkbp:fileExtension
.v
.vh
gptkbp:firstAppearance
1984
https://www.w3.org/2000/01/rdf-schema#label
Verilog hardware description language
gptkbp:influenced
gptkb:SystemVerilog
gptkb:Bluespec_SystemVerilog
gptkb:Chisel
e language
gptkbp:influencedBy
gptkb:C_programming_language
gptkb:Ada
gptkb:VHDL
gptkbp:latestReleaseVersion
gptkb:IEEE_1364-2005
gptkbp:notableFeature
event-driven simulation
hierarchical design
timing control
module-based design
synthesizable subset
gptkbp:openSource
gptkb:Cocotb
gptkb:Icarus_Verilog
gptkb:Verilator
gptkbp:paradigm
imperative
concurrent
structural
object-oriented (limited)
gptkbp:proprietary
gptkb:Cadence_Incisive
gptkb:Synopsys_VCS
gptkb:Mentor_ModelSim
gptkbp:standardizedBy
gptkb:IEEE
1995
gptkbp:standardNumber
gptkb:IEEE_1364
gptkbp:successor
gptkb:SystemVerilog
gptkbp:supports
RTL design
behavioral modeling
gate-level modeling
testbenches
switch-level modeling
gptkbp:usedFor
simulation of digital circuits
design of digital circuits
synthesis of digital circuits
gptkbp:website
https://ieeexplore.ieee.org/document/157878
gptkbp:bfsParent
gptkb:Phil_Moorby
gptkb:Prabhu_Goel
gptkbp:bfsLayer
6