|
gptkbp:instanceOf
|
hardware description language
|
|
gptkbp:category
|
hardware description language
|
|
gptkbp:competitor
|
gptkb:VHDL
|
|
gptkbp:developedBy
|
gptkb:Gateway_Design_Automation
gptkb:Phil_Moorby
gptkb:Prabhu_Goel
|
|
gptkbp:domain
|
electronic design automation
|
|
gptkbp:feature
|
gptkb:Verilog-1995
gptkb:Verilog-2001
gptkb:Verilog-2005
|
|
gptkbp:fileExtension
|
.v
.vh
|
|
gptkbp:hasFeature
|
gptkb:IEEE_1364-1995
gptkb:IEEE_1364-2001
gptkb:IEEE_1364-2005
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
Verilog
|
|
gptkbp:influenced
|
gptkb:SystemVerilog
gptkb:Bluespec_SystemVerilog
gptkb:Chisel
e language
|
|
gptkbp:influencedBy
|
gptkb:C_programming_language
gptkb:Ada
|
|
gptkbp:introducedIn
|
1984
|
|
gptkbp:license
|
gptkb:standard
|
|
gptkbp:notableFor
|
gptkb:Altera_Quartus
gptkb:Cadence_Incisive
gptkb:Icarus_Verilog
gptkb:ModelSim
gptkb:Synopsys_VCS
gptkb:Xilinx_Vivado
|
|
gptkbp:paradigm
|
imperative
event-driven
concurrent
structural
object-oriented (limited)
|
|
gptkbp:primaryUse
|
ASIC design
FPGA design
|
|
gptkbp:similarTo
|
C
|
|
gptkbp:standardizedBy
|
gptkb:IEEE
1995
yes
|
|
gptkbp:standardNumber
|
gptkb:IEEE_1364
|
|
gptkbp:successor
|
gptkb:SystemVerilog
|
|
gptkbp:supports
|
RTL design
behavioral modeling
gate-level modeling
testbenches
|
|
gptkbp:usedFor
|
design of digital circuits
modeling electronic systems
simulation of hardware
synthesis of hardware
|
|
gptkbp:website
|
https://ieeexplore.ieee.org/document/1620780
|
|
gptkbp:bfsParent
|
gptkb:list
gptkb:programming_language
|
|
gptkbp:bfsLayer
|
4
|