Statements (29)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:simulation
|
| gptkbp:category |
electronic design automation
|
| gptkbp:developedBy |
gptkb:Synopsys
|
| gptkbp:firstReleased |
1990s
|
| gptkbp:fullName |
gptkb:Verilog_Compiler_Simulator
|
| https://www.w3.org/2000/01/rdf-schema#label |
Synopsys VCS
|
| gptkbp:latestReleaseVersion |
2020s
|
| gptkbp:license |
proprietary
|
| gptkbp:platform |
gptkb:Windows
gptkb:Linux |
| gptkbp:supports |
gptkb:SVA
gptkb:SystemC gptkb:UVM debugging multi-core processing code coverage parallel simulation mixed-language simulation waveform viewing |
| gptkbp:usedBy |
semiconductor industry
verification engineers chip designers |
| gptkbp:usedFor |
SystemVerilog simulation
VHDL simulation Verilog simulation digital circuit verification |
| gptkbp:website |
https://www.synopsys.com/verification/simulation/vcs.html
|
| gptkbp:bfsParent |
gptkb:Verilog
|
| gptkbp:bfsLayer |
5
|