Statements (28)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
Electronic Design Automation software
|
| gptkbp:acquiredBy |
gptkb:Intel
|
| gptkbp:acquisitionYear |
2015
|
| gptkbp:developedBy |
gptkb:Intel
gptkb:Altera |
| https://www.w3.org/2000/01/rdf-schema#label |
Altera Quartus
|
| gptkbp:includes |
IP core integration
Place and route tools Simulation tools Synthesis tools Timing analysis |
| gptkbp:latestReleaseVersion |
gptkb:Quartus_Prime
|
| gptkbp:license |
Proprietary
|
| gptkbp:operatingSystem |
gptkb:Windows
gptkb:Linux |
| gptkbp:platform |
gptkb:Altera_FPGA
gptkb:Intel_FPGA |
| gptkbp:previousName |
gptkb:MAX+PLUS_II
gptkb:Quartus_II |
| gptkbp:releaseYear |
2001
|
| gptkbp:supports |
gptkb:VHDL
gptkb:Verilog gptkb:SystemVerilog |
| gptkbp:usedFor |
FPGA design
CPLD design |
| gptkbp:website |
https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html
|
| gptkbp:bfsParent |
gptkb:Verilog
|
| gptkbp:bfsLayer |
5
|