Statements (96)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
Electronic Design Automation software
|
| gptkbp:developedBy |
gptkb:Xilinx
|
| gptkbp:firstReleased |
2012
|
| gptkbp:hasFeature |
gptkb:graphical_user_interface
Project management Multi-language support Batch processing Debugging tools Resource optimization Scripting automation Version control integration High-level synthesis Timing analysis Power analysis Partial reconfiguration Floorplanning Constraint management Device programming IP catalog Incremental compilation Resource estimation Bitstream encryption Block design environment Constraint validation Cross-probing Design analysis Design checkpointing Design constraints management Design documentation generation Design export Design migration from ISE Design partitioning Design reuse Design rule checks Design summary Design synthesis reports Device support updates Error and warning reporting Functional simulation Hardware co-simulation Hardware/software co-design Hierarchical design support IP core customization IP integrator automation IP packaging Implementation reports On-chip debugging Post-implementation simulation Power optimization Power reports Project archiving Remote hardware management Resource utilization reports Schematic viewer Simulation acceleration System-level design Third-party tool integration Timing closure assistance Timing reports Timing simulation User constraint files Waveform viewer |
| https://www.w3.org/2000/01/rdf-schema#label |
Vivado Design Suite
|
| gptkbp:latestReleaseVersion |
2023.1
|
| gptkbp:license |
Proprietary
|
| gptkbp:operatingSystem |
gptkb:Windows
gptkb:Linux |
| gptkbp:platform |
gptkb:Xilinx_UltraScale+_FPGAs
gptkb:Xilinx_UltraScale_FPGAs gptkb:Xilinx_7_Series_FPGAs gptkb:Xilinx_Zynq-7000_SoC |
| gptkbp:programmingLanguage |
gptkb:Tcl
gptkb:C++ |
| gptkbp:replacedBy |
gptkb:ISE_Design_Suite
|
| gptkbp:supportsLanguage |
gptkb:Tcl
gptkb:VHDL gptkb:Verilog gptkb:C++ gptkb:SystemVerilog C |
| gptkbp:usedFor |
SoC design
Synthesis Implementation FPGA design Bitstream generation IP core integration Hardware description language simulation |
| gptkbp:uses |
gptkb:Vivado_HLS
gptkb:Vivado_IP_Integrator gptkb:Vivado_Simulator gptkb:Vivado_Implementation gptkb:Vivado_Logic_Analyzer gptkb:Vivado_Synthesis |
| gptkbp:website |
https://www.xilinx.com/products/design-tools/vivado.html
|
| gptkbp:bfsParent |
gptkb:Xilinx_Vivado
|
| gptkbp:bfsLayer |
6
|