Statements (51)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
EDA tool feature
|
| gptkbp:developedBy |
gptkb:Xilinx
|
| gptkbp:feature |
gptkb:Design_Rule_Checking
Floorplanning Timing Closure Resource Utilization Analysis Power Analysis Hierarchical Design Support Utilization Reports Batch Mode Operation Clock Domain Crossing Analysis Constraint Management Cross-probing with Vivado IDE Design Checkpoints Design Constraints (XDC) Support Design Partitioning Error and Warning Reporting IO Planning IP Integration Incremental Implementation Multi-threaded Processing Netlist Optimization Physical Optimization Pin Assignment Power Reports Schematic Viewer Support for Block Design Containers Support for Design Preservation Support for ECO (Engineering Change Order) flows Support for Hierarchical Design Flows Support for Partial Reconfiguration Tcl Scripting Support Timing Reports |
| gptkbp:format |
gptkb:Bitstream
Reports HDL Netlist Placed and Routed Netlist |
| https://www.w3.org/2000/01/rdf-schema#label |
Vivado Implementation
|
| gptkbp:partOf |
Xilinx Vivado Design Suite
|
| gptkbp:platform |
gptkb:Xilinx_UltraScale+_FPGAs
gptkb:Xilinx_UltraScale_FPGAs gptkb:Xilinx_7_Series_FPGAs |
| gptkbp:usedFor |
Synthesis
FPGA design Place and Route Timing Analysis Bitstream Generation |
| gptkbp:bfsParent |
gptkb:Vivado
gptkb:Vivado_Design_Suite |
| gptkbp:bfsLayer |
7
|