Statements (29)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:software
|
| gptkbp:category |
gptkb:FPGA_design_tool
DSP development tool |
| gptkbp:developedBy |
gptkb:Xilinx
|
| gptkbp:enables |
rapid prototyping
automatic code generation hardware co-simulation |
| gptkbp:firstReleased |
2001
|
| gptkbp:format |
gptkb:VHDL
gptkb:Verilog Netlist |
| gptkbp:generation |
HDL code
|
| gptkbp:integratesWith |
gptkb:MATLAB
gptkb:Simulink |
| gptkbp:latestReleaseVersion |
2023.1
|
| gptkbp:license |
proprietary
|
| gptkbp:operatingSystem |
gptkb:Windows
|
| gptkbp:platform |
gptkb:FPGA
|
| gptkbp:supports |
gptkb:Vivado_Design_Suite
gptkb:Xilinx_FPGAs gptkb:ISE_Design_Suite floating-point arithmetic model-based design fixed-point arithmetic |
| gptkbp:usedFor |
digital signal processing
|
| gptkbp:website |
https://www.xilinx.com/products/design-tools/vivado/integration/sysgen.html
|
| gptkbp:bfsParent |
gptkb:Vivado_Design_Suite_HL_WebPACK_Edition
|
| gptkbp:bfsLayer |
9
|
| https://www.w3.org/2000/01/rdf-schema#label |
System Generator for DSP
|