|
gptkbp:instanceOf
|
gptkb:standard
|
|
gptkbp:covers
|
gptkb:hardware_description_language
gptkb:hardware_verification_language
|
|
gptkbp:firstPublished
|
2005
|
|
gptkbp:focusesOn
|
gptkb:SystemVerilog
|
|
gptkbp:fullName
|
gptkb:IEEE_Standard_for_SystemVerilog—Unified_Hardware_Design,_Specification,_and_Verification_Language
|
|
gptkbp:language
|
English
|
|
gptkbp:latestReleaseVersion
|
gptkb:IEEE_1800-2017
|
|
gptkbp:publishedBy
|
gptkb:Institute_of_Electrical_and_Electronics_Engineers
|
|
gptkbp:relatedStandard
|
gptkb:IEEE_1364
gptkb:IEEE_1800.2
|
|
gptkbp:status
|
active
|
|
gptkbp:updated
|
gptkb:IEEE_1364
|
|
gptkbp:usedFor
|
digital circuit design
hardware verification
|
|
gptkbp:website
|
https://standards.ieee.org/standard/1800-2017.html
|
|
gptkbp:bfsParent
|
gptkb:SystemVerilog
gptkb:IEEE_1364
gptkb:SystemVerilog_Assertions
gptkb:SystemC_Language_Reference_Manual
|
|
gptkbp:bfsLayer
|
8
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
IEEE 1800
|