Statements (25)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:software
|
| gptkbp:abbreviation |
VCS
|
| gptkbp:category |
gptkb:Electronic_Design_Automation
electronic design automation |
| gptkbp:developedBy |
gptkb:Cadence_Design_Systems
|
| gptkbp:firstReleased |
1990s
|
| https://www.w3.org/2000/01/rdf-schema#label |
Verilog Compiler Simulator
|
| gptkbp:language |
gptkb:Verilog
gptkb:SystemVerilog |
| gptkbp:license |
proprietary
|
| gptkbp:platform |
gptkb:Windows
gptkb:Linux |
| gptkbp:supports |
gptkb:UVM
debugging code coverage mixed-language simulation waveform viewing assertion-based verification testbench automation |
| gptkbp:usedFor |
logic simulation
functional verification simulation of Verilog hardware description language |
| gptkbp:website |
https://www.cadence.com/en_US/home/tools/system-design-and-verification/simulation-and-testbench-verification/vcs.html
|
| gptkbp:bfsParent |
gptkb:Synopsys_VCS
|
| gptkbp:bfsLayer |
6
|