Statements (23)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:architecture |
gptkb:RISC_(Reduced_Instruction_Set_Computer)
|
| gptkbp:designer |
gptkb:David_Patterson
gptkb:Carlo_H._Séquin |
| gptkbp:developedBy |
gptkb:University_of_California,_Berkeley
|
| gptkbp:influenced |
gptkb:SPARC_architecture
MIPS architecture |
| gptkbp:instructionSet |
32 instructions
|
| gptkbp:introducedIn |
1983
|
| gptkbp:length |
32-bit
|
| gptkbp:manufacturer |
gptkb:MOSIS
|
| gptkbp:notableFor |
pioneering RISC architecture
|
| gptkbp:predecessor |
gptkb:RISC_I_processor
|
| gptkbp:registration |
138 registers
|
| gptkbp:size |
6 mm²
|
| gptkbp:speed |
3 MHz
|
| gptkbp:successor |
gptkb:SOAR_processor
|
| gptkbp:technology |
3 µm CMOS
|
| gptkbp:transistorCount |
40,760
|
| gptkbp:usedIn |
academic research
|
| gptkbp:bfsParent |
gptkb:Berkeley_RISC
|
| gptkbp:bfsLayer |
7
|
| https://www.w3.org/2000/01/rdf-schema#label |
RISC II processor
|