Statements (18)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:software
|
| gptkbp:author |
gptkb:Jan_Decaluwe
|
| gptkbp:category |
gptkb:hardware_description_language
gptkb:electronic_design_automation |
| gptkbp:convertedTo |
gptkb:VHDL
gptkb:Verilog |
| gptkbp:firstReleased |
2003
|
| gptkbp:license |
gptkb:LGPL
|
| gptkbp:openSource |
true
|
| gptkbp:programmingLanguage |
gptkb:Python
|
| gptkbp:usedFor |
digital design
ASIC design FPGA design hardware description |
| gptkbp:website |
http://www.myhdl.org/
|
| gptkbp:bfsParent |
gptkb:VHSIC_Hardware_Description_Language
|
| gptkbp:bfsLayer |
7
|
| https://www.w3.org/2000/01/rdf-schema#label |
MyHDL
|