ARM SVE
E732964
ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
All labels observed (6)
| Label | Occurrences |
|---|---|
| ARM SVE2 | 2 |
| ARM Scalable Vector Extension | 2 |
| ARM SVE canonical | 1 |
| SVE (Scalable Vector Extension) | 1 |
| Scalable Vector Extension | 1 |
| Scalable Vector Extension 2 | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8414860 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: ARM SVE Context triple: [NEON SIMD, distinctFrom, ARM SVE]
-
A.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
B.
ARMv8-A
ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
-
C.
ARMv9-A
ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
-
D.
NEON SIMD
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
-
E.
AVX-512
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: ARM SVE Target entity description: ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
-
A.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
B.
ARMv8-A
ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
-
C.
ARMv9-A
ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
-
D.
NEON SIMD
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
-
E.
AVX-512
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
- F. None of above. chosen
Statements (51)
| Predicate | Object |
|---|---|
| instanceOf | instruction set architecture extension ⓘ |
| abbreviation | SVE ⓘ |
| architectureFamily | ARMv8-A ⓘ |
| designGoal |
enable portable performance across different vector widths
ⓘ
improve SIMD performance for HPC workloads ⓘ support auto-vectorization by compilers ⓘ |
| developer | Arm Ltd. ⓘ |
| executionMode | AArch64 only ⓘ |
| fullName |
ARM Scalable Vector Extension
ⓘ
linked to:
ARM SVE
|
| includesFeature |
predicate registers
ⓘ
vector arithmetic instructions ⓘ vector bitwise operations ⓘ vector compare instructions ⓘ vector condition flags ⓘ vector load/store instructions ⓘ vector permute instructions ⓘ vector reduction instructions ⓘ |
| introducedFor |
ARMv8-A AArch64 state
ⓘ
linked to:
ARMv8-A
|
| keyFeature |
gather-load and scatter-store operations
ⓘ
length-agnostic vector programming model ⓘ per-lane predication masks ⓘ scalable vector length ⓘ support for integer and floating-point vector operations ⓘ vector predication ⓘ vectorization of loops with unknown trip counts ⓘ vectorized complex arithmetic support ⓘ vectorized gather-scatter for irregular memory access patterns ⓘ vectorized horizontal operations ⓘ vectorized reduction operations ⓘ |
| programmingModel | vector-length agnostic ⓘ |
| registerCount | 32 vector registers ⓘ |
| registerType | vector registers ⓘ |
| registerWidth | implementation-defined vector length ⓘ |
| standardizedBy | Arm ARM (Architecture Reference Manual) for ARMv8-A ⓘ |
| successor |
ARM SVE2
ⓘ
linked to:
ARM SVE
|
| supportsDataTypes |
16-bit floating point
ⓘ
16-bit integer ⓘ 32-bit floating point ⓘ 32-bit integer ⓘ 64-bit floating point ⓘ 64-bit integer ⓘ 8-bit integer ⓘ |
| targetDomain |
data-intensive workloads
ⓘ
high-performance computing ⓘ |
| toolchainSupport |
Arm Compiler for Linux
ⓘ
GCC ⓘ LLVM/Clang ⓘ
linked to:
LLVM
|
| usedIn |
Fugaku supercomputer
ⓘ
Fujitsu A64FX processor ⓘ
linked to:
Fujitsu A64FX
|
| vectorLengthGranularityBits | 128 ⓘ |
| vectorLengthRangeBits | 128–2048 ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: ARM SVE Description of subject: ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
Referenced by (8)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: ARM SVE
linked to: ARM SVE
subject linked to:
Fugaku supercomputer
linked to: ARM SVE
linked to: ARM SVE
linked to: ARM SVE