Triple

T8414860
Position Surface form Disambiguated ID Type / Status
Subject NEON SIMD E198707 entity
Predicate distinctFrom P1612 FINISHED
Object ARM SVE
ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
E732964 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: ARM SVE | Statement: [NEON SIMD, distinctFrom, ARM SVE]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: ARM SVE
Context triple: [NEON SIMD, distinctFrom, ARM SVE]
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. ARMv8-A
    ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
  • C. ARMv9-A
    ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
  • D. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • E. AVX-512
    AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: ARM SVE
Triple: [NEON SIMD, distinctFrom, ARM SVE]
Generated description
ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: ARM SVE
Target entity description: ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. ARMv8-A
    ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
  • C. ARMv9-A
    ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
  • D. NEON SIMD
    NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • E. AVX-512
    AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca831201b481909e137936ef99ff11 completed March 30, 2026, 2:05 p.m.
NER Named-entity recognition batch_69cb83e443a08190983d9a0a61e0f781 completed March 31, 2026, 8:20 a.m.
NED1 Entity disambiguation (via context triple) batch_69ce032a25ec819094c6346eb2a7f973 completed April 2, 2026, 5:48 a.m.
NEDg Description generation batch_69ce0781859c8190bb92f41c00af459b completed April 2, 2026, 6:06 a.m.
NED2 Entity disambiguation (via description) batch_69ce089d09c08190ba321aed4044a862 completed April 2, 2026, 6:11 a.m.
Created at: March 30, 2026, 6:06 p.m.