instructionSetExtensions
P74581
predicate
Indicates that one entity defines, supports, or includes additional instruction set features or extensions relative to another.
All labels observed (9)
| Label | Occurrences |
|---|---|
| supportsInstructionExtensions | 10 |
| instructionSetExtensions canonical | 7 |
| supportsISAExtension | 7 |
| introducedInstructionSetExtension | 3 |
| SIMDExtension | 1 |
| SIMDExtensions | 1 |
| hasEnhancedInstructionSetComparedTo | 1 |
| processorExtension | 1 |
| supportsExtendedInstructionSet | 1 |
Description generation (PDg)
The one-sentence description above was generated by prompting gpt-5.1 with the predicate name and this instruction.
Instruction
Given a predicate that represents a relationship or action between entities, generate a one-sentence description explaining its meaning. # Instructions Focus on describing the relationship, not the entities themselves. # Response Format Begin the description with \' Indicates...\'
Input
Predicate: instructionSetExtensions
Generated description
Indicates that one entity defines, supports, or includes additional instruction set features or extensions relative to another.
Sample triples (32)
| Subject | Object |
|---|---|
| P54C | none beyond baseline Pentium ⓘ |
| Zilog Z80 | Intel 8080 via predicate surface "hasEnhancedInstructionSetComparedTo" ⓘ |
| QEMU RISC-V target |
RISC-V I base integer extension
via predicate surface "supportsISAExtension"
ⓘ
linked to:
RISC-V
|
| QEMU RISC-V target | RISC-V M integer multiplication and division extension via predicate surface "supportsISAExtension" ⓘ |
| QEMU RISC-V target | RISC-V A atomic extension via predicate surface "supportsISAExtension" ⓘ |
| QEMU RISC-V target | RISC-V F single-precision floating-point extension via predicate surface "supportsISAExtension" ⓘ |
| QEMU RISC-V target | RISC-V D double-precision floating-point extension via predicate surface "supportsISAExtension" ⓘ |
| QEMU RISC-V target |
RISC-V C compressed extension
via predicate surface "supportsISAExtension"
ⓘ
linked to:
RISC-V
|
| QEMU RISC-V target | RISC-V privileged architecture via predicate surface "supportsISAExtension" ⓘ |
|
Fugaku
linked to:
Fugaku supercomputer
|
Scalable Vector Extension
via predicate surface "processorExtension"
ⓘ
linked to:
ARM SVE
|
| AMD K6-2 | 3DNow! via predicate surface "introducedInstructionSetExtension" ⓘ |
| AMD K6-2 | 3DNow! via predicate surface "SIMDExtension" ⓘ |
| Prescott | SSE3 via predicate surface "introducedInstructionSetExtension" ⓘ |
| Prescott | Intel 64 (on some models) via predicate surface "introducedInstructionSetExtension" ⓘ |
| Intel Core m3-7Y30 |
Intel SSE4.1
ⓘ
linked to:
SSE4.1
|
| Intel Core m3-7Y30 |
Intel SSE4.2
ⓘ
linked to:
SSE4.2
|
| Intel Core m3-7Y30 | Intel AVX2 ⓘ |
| Intel Core i7-7Y75 | SSE4.1 ⓘ |
| Intel Core i7-7Y75 | SSE4.2 ⓘ |
| Intel Core i7-7Y75 | AVX2 ⓘ |
| IBM Gekko | custom SIMD instructions for graphics and media via predicate surface "SIMDExtensions" ⓘ |
| KL10 | yes via predicate surface "supportsExtendedInstructionSet" ⓘ |
| Intel Pentium Gold 4415Y | SSE4.1 via predicate surface "supportsInstructionExtensions" ⓘ |
| Intel Pentium Gold 4415Y | SSE4.2 via predicate surface "supportsInstructionExtensions" ⓘ |
| Intel Pentium Gold 4415Y | AVX2 via predicate surface "supportsInstructionExtensions" ⓘ |
| Intel Pentium Gold 4415Y | Intel AES-NI via predicate surface "supportsInstructionExtensions" ⓘ |
| Intel Pentium Gold 4415Y |
Intel VT-x with EPT
via predicate surface "supportsInstructionExtensions"
ⓘ
linked to:
Intel VT-x
|
| Regor (cut-down) | SSE via predicate surface "supportsInstructionExtensions" ⓘ |
| Regor (cut-down) | SSE2 via predicate surface "supportsInstructionExtensions" ⓘ |
| Regor (cut-down) | SSE3 via predicate surface "supportsInstructionExtensions" ⓘ |
| Regor (cut-down) | SSE4A via predicate surface "supportsInstructionExtensions" ⓘ |
| Regor (cut-down) | AMD64 via predicate surface "supportsInstructionExtensions" ⓘ |