SPARC microprocessor architecture
E68040
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
All labels observed (13)
| Label | Occurrences |
|---|---|
| SPARC | 30 |
| SPARC architecture | 14 |
| SPARC V9 | 5 |
| SPARC V8 | 3 |
| SPARC V7 | 2 |
| Gaisler Research (LEON cores) | 1 |
| LEON processor family | 1 |
| SPARC instruction set architecture | 1 |
| SPARC microprocessor architecture canonical | 1 |
| SPARC platform | 1 |
| SPARC processor standard | 1 |
| SPARC64 | 1 |
| Sun SPARCserver architecture | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T542290 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: SPARC microprocessor architecture Context triple: [Sun Microsystems, developerOf, SPARC microprocessor architecture]
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
Motorola 88000 family
The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
-
C.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
-
D.
Transmeta
Transmeta was an innovative semiconductor company best known for its low-power x86-compatible microprocessors and for employing Linux creator Linus Torvalds.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: SPARC microprocessor architecture Target entity description: The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
Motorola 88000 family
The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
-
C.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
-
D.
Transmeta
Transmeta was an innovative semiconductor company best known for its low-power x86-compatible microprocessors and for employing Linux creator Linus Torvalds.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
Statements (68)
| Predicate | Object |
|---|---|
| instanceOf |
RISC architecture
ⓘ
SPARC version ⓘ SPARC version ⓘ SPARC version ⓘ instruction set architecture ⓘ |
| applicationDomain |
embedded processors
ⓘ
server processors ⓘ space-grade processors ⓘ workstation processors ⓘ |
| architectureStyle | load-store architecture ⓘ |
| bitWidth |
32-bit
ⓘ
32-bit ⓘ 32-bit ⓘ 64-bit ⓘ 64-bit ⓘ |
| category | RISC instruction set architecture ⓘ |
| designer | Sun Microsystems ⓘ |
| feature |
64-bit integer registers
ⓘ
64-bit virtual address space ⓘ annulled branch delay slot ⓘ modular implementation specification ⓘ privileged and user modes ⓘ register window mechanism to reduce procedure call overhead ⓘ scalable multiprocessing support ⓘ separate integer and floating-point register sets ⓘ trap-based system calls ⓘ well-defined supervisor mode ⓘ |
| firstAppeared | 1987 ⓘ |
| fullName |
Microprocessor without Interlocked Pipeline Stages
ⓘ
surface form:
Scalable Processor Architecture
|
| governedBy | SPARC International ⓘ |
| influenced |
SPARC microprocessor architecture
self-linksurface differs
ⓘ
surface form:
LEON processor family
|
| influencedBy |
Berkeley RISC projects
ⓘ
surface form:
Berkeley RISC
RISC I ⓘ RISC II ⓘ |
| licenseModel | open architecture specification ⓘ |
| purpose |
enterprise servers
ⓘ
high-performance computing ⓘ workstations ⓘ |
| registerFile | 32 general-purpose registers per window ⓘ |
| standardizedBy | SPARC International ⓘ |
| supports |
IEEE 754 floating‑point arithmetic standard
ⓘ
surface form:
IEEE 754 floating-point
atomic memory operations ⓘ big-endian mode ⓘ cache coherence protocols (implementation-dependent) ⓘ delayed branches ⓘ hardware multiply and divide (in later versions) ⓘ little-endian mode ⓘ multiprocessing ⓘ multithreading ⓘ register windows ⓘ virtual memory ⓘ |
| typicalImplementation |
out-of-order execution (in high-end cores)
ⓘ
superscalar pipelines ⓘ |
| usedBy |
Fujitsu Limited
ⓘ
surface form:
Fujitsu
SPARC microprocessor architecture self-linksurface differs ⓘ
surface form:
Gaisler Research (LEON cores)
Oracle Corporation ⓘ Sun Microsystems ⓘ Texas Instruments ⓘ
surface form:
Texas Instruments (embedded SPARC)
|
| usedIn |
Fujitsu SPARC servers
ⓘ
Oracle SPARC servers ⓘ Sun Enterprise servers ⓘ SPARCstation ⓘ
surface form:
Sun SPARCstation workstations
Sun-4 workstation ⓘ
surface form:
Sun-4 systems
embedded systems ⓘ space-qualified processors ⓘ |
| variant |
SPARC microprocessor architecture
self-linksurface differs
ⓘ
surface form:
SPARC V7
SPARC microprocessor architecture self-linksurface differs ⓘ
surface form:
SPARC V8
SPARC microprocessor architecture self-linksurface differs ⓘ
surface form:
SPARC V9
|
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: SPARC microprocessor architecture Description of subject: The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
Referenced by (62)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC
subject surface form:
Motorola 88000
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC
subject surface form:
Solaris
this entity surface form:
SPARC
SPARC microprocessor architecture
→
influenced
→
SPARC microprocessor architecture
self-linksurface differs
ⓘ
subject surface form:
SPARC
this entity surface form:
LEON processor family
SPARC microprocessor architecture
→
variant
→
SPARC microprocessor architecture
self-linksurface differs
ⓘ
subject surface form:
SPARC
this entity surface form:
SPARC V7
SPARC microprocessor architecture
→
variant
→
SPARC microprocessor architecture
self-linksurface differs
ⓘ
subject surface form:
SPARC
this entity surface form:
SPARC V8
SPARC microprocessor architecture
→
variant
→
SPARC microprocessor architecture
self-linksurface differs
ⓘ
subject surface form:
SPARC
this entity surface form:
SPARC V9
SPARC microprocessor architecture
→
usedBy
→
SPARC microprocessor architecture
self-linksurface differs
ⓘ
subject surface form:
SPARC
this entity surface form:
Gaisler Research (LEON cores)
this entity surface form:
SPARC
this entity surface form:
SPARC V9
this entity surface form:
SPARC
this entity surface form:
SPARC architecture
this entity surface form:
SPARC V7
this entity surface form:
SPARC V8
this entity surface form:
SPARC architecture
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
Microprocessor without Interlocked Pipeline Stages
→
influenced
→
SPARC microprocessor architecture
ⓘ
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
Sun SPARCserver architecture
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC
this entity surface form:
SPARC architecture
this entity surface form:
SPARC architecture
this entity surface form:
SPARC processor standard
this entity surface form:
SPARC instruction set architecture
this entity surface form:
SPARC V8
this entity surface form:
SPARC V9
this entity surface form:
SPARC architecture
this entity surface form:
SPARC
this entity surface form:
SPARC