Triple

T3244653
Position Surface form Disambiguated ID Type / Status
Subject SPARC E68040 entity
Predicate usedBy P260 FINISHED
Object Gaisler Research (LEON cores)
Gaisler Research’s LEON cores are a family of radiation-tolerant, open SPARC processor designs widely used in space and aerospace applications.
E68040 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Gaisler Research (LEON cores) | Statement: [SPARC, usedBy, Gaisler Research (LEON cores)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Gaisler Research (LEON cores)
Context triple: [SPARC, usedBy, Gaisler Research (LEON cores)]
  • A. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • B. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • C. Transmeta
    Transmeta was an innovative semiconductor company best known for its low-power x86-compatible microprocessors and for employing Linux creator Linus Torvalds.
  • D. Berkeley RISC projects
    The Berkeley RISC projects were pioneering academic research efforts at the University of California, Berkeley that developed early Reduced Instruction Set Computer architectures, profoundly influencing modern processor design.
  • E. Crusoe microprocessor
    The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Gaisler Research (LEON cores)
Triple: [SPARC, usedBy, Gaisler Research (LEON cores)]
Generated description
Gaisler Research’s LEON cores are a family of radiation-tolerant, open SPARC processor designs widely used in space and aerospace applications.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: Gaisler Research (LEON cores)
Target entity description: Gaisler Research’s LEON cores are a family of radiation-tolerant, open SPARC processor designs widely used in space and aerospace applications.
  • A. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • B. SPARC microprocessor architecture chosen
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • C. Transmeta
    Transmeta was an innovative semiconductor company best known for its low-power x86-compatible microprocessors and for employing Linux creator Linus Torvalds.
  • D. Berkeley RISC projects
    The Berkeley RISC projects were pioneering academic research efforts at the University of California, Berkeley that developed early Reduced Instruction Set Computer architectures, profoundly influencing modern processor design.
  • E. Crusoe microprocessor
    The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
  • F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ad858e4c708190aa31d486cfee8a6a completed March 8, 2026, 2:19 p.m.
NER Named-entity recognition batch_69adaf1982448190b3d60c9e4471421f completed March 8, 2026, 5:17 p.m.
NED1 Entity disambiguation (via context triple) batch_69b2775be7c88190ba60b191f1c51e19 completed March 12, 2026, 8:20 a.m.
NEDg Description generation batch_69b278471ee48190918dd503d1bffd7d completed March 12, 2026, 8:24 a.m.
NED2 Entity disambiguation (via description) batch_69b278a64ae48190a00dbeff59ad9d6b completed March 12, 2026, 8:26 a.m.
Created at: March 8, 2026, 3:08 p.m.