Intel AES-NI
E163102
Intel AES-NI is a set of hardware instructions introduced by Intel to accelerate and secure AES encryption and decryption operations in modern processors.
All labels observed (3)
| Label | Occurrences |
|---|---|
| AES-NI | 4 |
| Intel AES-NI canonical | 2 |
| Intel Advanced Encryption Standard New Instructions | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1422857 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
Target entity: Intel AES-NI Context triple: [Intel Xeon, supportsFeature, Intel AES-NI]
-
A.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
B.
AMD processors
AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
-
C.
AMD64 architecture
The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
Intel Inside
Intel Inside is a famous marketing slogan and branding campaign used to promote personal computers powered by Intel processors.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Target entity: Intel AES-NI Target entity description: Intel AES-NI is a set of hardware instructions introduced by Intel to accelerate and secure AES encryption and decryption operations in modern processors.
-
A.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
B.
AMD processors
AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
-
C.
AMD64 architecture
The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
Intel Inside
Intel Inside is a famous marketing slogan and branding campaign used to promote personal computers powered by Intel processors.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
Intel technology
ⓘ
instruction set extension ⓘ |
| abbreviation |
Intel AES-NI
self-linksurface differs
ⓘ
surface form:
AES-NI
|
| appliesToAlgorithm | Advanced Encryption Standard ⓘ |
| category |
cryptographic instruction set
ⓘ
hardware acceleration ⓘ |
| compatibleWith |
Linux kernel crypto API
ⓘ
OpenSSL ⓘ Windows CryptoAPI ⓘ |
| detectedBy | CPUID instruction ⓘ |
| developer |
Intel Corporation
ⓘ
surface form:
Intel
|
| featureFlag | AES ⓘ |
| fullName |
Intel AES-NI
self-linksurface differs
ⓘ
surface form:
Intel Advanced Encryption Standard New Instructions
|
| improves |
AES latency
ⓘ
AES throughput ⓘ |
| includesInstruction |
AESDEC
ⓘ
AESDECLAST ⓘ AESENC ⓘ AESENCLAST ⓘ AESIMC ⓘ AESKEYGENASSIST ⓘ |
| influenced | hardware AES support in other CPU architectures ⓘ |
| introducedByMicroarchitecture | Westmere ⓘ |
| introducedYear | 2010 ⓘ |
| purpose |
accelerate AES decryption
ⓘ
accelerate AES encryption ⓘ improve security of AES implementations ⓘ |
| reduces |
CPU cycles per AES block
ⓘ
side-channel attack surface compared to some software AES implementations ⓘ |
| relatedTo |
Intel AVX
ⓘ
Intel SHA Extensions ⓘ |
| securityBenefit |
helps mitigate cache-timing attacks on AES compared to some software-only implementations
ⓘ
reduces need for table-based AES implementations ⓘ |
| specifiedIn |
Intel Architecture Software Developer’s Manual
ⓘ
surface form:
Intel 64 and IA-32 Architectures Software Developer’s Manual
|
| standardizedIn | x86 ISA extensions ⓘ |
| supportedByVendor |
Advanced Micro Devices
ⓘ
surface form:
AMD
|
| supportsKeySize |
128-bit AES
ⓘ
192-bit AES ⓘ 256-bit AES ⓘ |
| targetArchitecture |
x86
ⓘ
x86-64 ⓘ |
| usedFor |
TLS/SSL acceleration
ⓘ
VPN encryption ⓘ disk encryption ⓘ |
| usedIn |
Intel Atom
ⓘ
surface form:
Intel Atom processors
Intel Core processor family ⓘ
surface form:
Intel Core processors
Intel Xeon ⓘ
surface form:
Intel Xeon processors
|
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Subject: Intel AES-NI Description of subject: Intel AES-NI is a set of hardware instructions introduced by Intel to accelerate and secure AES encryption and decryption operations in modern processors.
Referenced by (7)
Full triples — surface form annotated when it differs from this entity's canonical label.