Statements (23)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:electronic_design_automation
|
| gptkbp:category |
EDA Tool
Logic Simulator |
| gptkbp:developedBy |
gptkb:Cadence_Design_Systems
|
| gptkbp:feature |
Mixed-Language Simulation
Accelerated Verification Low Power Simulation Parallel Simulation Unified Simulation Engine |
| gptkbp:platform |
gptkb:Windows
gptkb:Linux |
| gptkbp:predecessor |
gptkb:Incisive_Enterprise_Simulator
|
| gptkbp:supportsLanguage |
gptkb:VHDL
gptkb:Verilog gptkb:SystemC gptkb:SystemVerilog e Language |
| gptkbp:usedFor |
Digital Simulation
Mixed-Signal Simulation |
| gptkbp:website |
https://www.cadence.com/en_US/home/tools/system-design-and-verification/simulation-and-testbench-verification/xcelium-parallel-simulator.html
|
| gptkbp:bfsParent |
gptkb:Cadence_Design_Systems
|
| gptkbp:bfsLayer |
6
|
| https://www.w3.org/2000/01/rdf-schema#label |
Xcelium
|