Statements (20)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:announced |
2019
|
| gptkbp:application |
embedded systems
storage controllers |
| gptkbp:architecture |
gptkb:RISC-V
|
| gptkbp:designedFor |
high performance
low power |
| gptkbp:developedBy |
gptkb:Western_Digital
|
| gptkbp:github |
https://github.com/chipsalliance/Cores-SweRV
|
| gptkbp:heldBy |
gptkb:RV32IMC
|
| gptkbp:license |
gptkb:Apache_License_2.0
|
| gptkbp:openSource |
true
|
| gptkbp:partOf |
gptkb:SweRV_Core_family
|
| gptkbp:pipelineStages |
9
|
| gptkbp:supports |
compressed instructions
integer multiplication and division |
| gptkbp:width |
32-bit
|
| gptkbp:bfsParent |
gptkb:SweRV
|
| gptkbp:bfsLayer |
7
|
| https://www.w3.org/2000/01/rdf-schema#label |
SweRV Core EL2
|