Statements (19)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:application |
embedded systems
|
| gptkbp:architecture |
gptkb:RISC-V
|
| gptkbp:cache |
gptkb:Harvard_architecture
|
| gptkbp:developedBy |
gptkb:Western_Digital
|
| gptkbp:github |
https://github.com/chipsalliance/Cores-SweRV
|
| gptkbp:heldBy |
gptkb:RISC-V
|
| https://www.w3.org/2000/01/rdf-schema#label |
SweRV Core EH2
|
| gptkbp:license |
Apache 2.0
|
| gptkbp:notableProject |
gptkb:SweRV_Core_family
|
| gptkbp:openSource |
yes
|
| gptkbp:pipelineStages |
9
|
| gptkbp:releaseYear |
2019
|
| gptkbp:supports |
gptkb:RISC-V_Bitmanip_extension
gptkb:RV32IMC |
| gptkbp:width |
32-bit
dual-issue |
| gptkbp:bfsParent |
gptkb:SweRV
|
| gptkbp:bfsLayer |
7
|