Statements (20)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:architecture |
gptkb:OpenRISC
|
| gptkbp:cache |
instruction and data cache
|
| gptkbp:designedBy |
gptkb:OpenCores
|
| gptkbp:firstReleased |
2000
|
| gptkbp:floatingPointUnit |
optional
|
| gptkbp:hasConcept |
gptkb:RISC
|
| https://www.w3.org/2000/01/rdf-schema#label |
OR1200
|
| gptkbp:instructionSet |
gptkb:OpenRISC_1000
|
| gptkbp:license |
gptkb:LGPL
|
| gptkbp:MMU |
true
|
| gptkbp:openSource |
true
|
| gptkbp:pipelineStages |
5
|
| gptkbp:supportsHarvardArchitecture |
true
|
| gptkbp:usedIn |
embedded systems
|
| gptkbp:website |
https://opencores.org/projects/or1k
|
| gptkbp:width |
32
|
| gptkbp:writtenBy |
gptkb:Verilog
|
| gptkbp:bfsParent |
gptkb:OpenRISC
|
| gptkbp:bfsLayer |
6
|