Statements (50)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
electronic design automation
|
| gptkbp:alternativeName |
C-to-RTL
behavioral synthesis |
| gptkbp:commercialTools |
Cadence Stratus HLS
Intel HLS Compiler Mentor Catapult HLS Xilinx Vivado HLS |
| gptkbp:developedBy |
1980s
|
| gptkbp:enables |
resource sharing
hardware acceleration hardware/software co-design scheduling binding rapid prototyping hardware verification pipelining latency reduction system-level design IP core generation design space exploration allocation timing optimization algorithm-to-hardware mapping algorithmic optimization area optimization automatic hardware generation control logic generation datapath generation parallelism exploitation power optimization throughput improvement |
| gptkbp:field |
digital circuit design
|
| gptkbp:format |
gptkb:VHDL
gptkb:Verilog gptkb:RTL |
| https://www.w3.org/2000/01/rdf-schema#label |
High-Level Synthesis (HLS)
|
| gptkbp:language |
gptkb:SystemC
gptkb:C++ C |
| gptkbp:reduces |
design time
|
| gptkbp:relatedTo |
hardware description language
logic synthesis behavioral synthesis register-transfer level |
| gptkbp:usedFor |
hardware design
ASIC design FPGA design |
| gptkbp:bfsParent |
gptkb:Xilinx_FPGA
gptkb:Vivado_Design_Suite_HL_Design_Edition |
| gptkbp:bfsLayer |
7
|