Statements (49)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
electronic design automation
|
| gptkbp:alsoKnownAs |
HLS
|
| gptkbp:application |
ASIC design
FPGA design |
| gptkbp:challenge |
Verification
Resource optimization Debugging Quality of results |
| gptkbp:commercialTool |
Cadence Stratus HLS
Mentor Catapult HLS Xilinx Vivado HLS Synopsys Synphony C Compiler |
| gptkbp:defines |
The process of converting a high-level algorithmic description of hardware into a register-transfer level (RTL) implementation.
|
| gptkbp:developedBy |
1980s
|
| gptkbp:enables |
Algorithm-to-hardware mapping
Design space exploration Faster hardware design |
| gptkbp:field |
electronic design automation
Computer engineering Digital design |
| gptkbp:format |
gptkb:VHDL
gptkb:Verilog gptkb:RTL |
| gptkbp:goal |
Increase productivity
Enable higher abstraction in hardware design Reduce time-to-market |
| https://www.w3.org/2000/01/rdf-schema#label |
High-Level Synthesis
|
| gptkbp:language |
gptkb:SystemC
gptkb:C++ C |
| gptkbp:openSourceTool |
LegUp
OpenHLS ROCCC |
| gptkbp:output |
Hardware netlist
Synthesizable RTL code |
| gptkbp:processor |
gptkb:Binding
Scheduling Allocation Control synthesis Data path synthesis |
| gptkbp:relatedTo |
Logic synthesis
Hardware description language Behavioral synthesis |
| gptkbp:standardizedBy |
gptkb:IEEE
IEEE 1666 (SystemC) |
| gptkbp:usedBy |
Hardware designers
System architects |
| gptkbp:bfsParent |
gptkb:Vivado_Design_Suite_HL_System_Edition
|
| gptkbp:bfsLayer |
7
|