OpenRISC
E724163
OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
All labels observed (4)
| Label | Occurrences |
|---|---|
| LatticeMico32 soft core | 1 |
| OR1K architecture | 1 |
| OpenCores.org | 1 |
| OpenRISC canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8285572 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: OpenRISC Context triple: [QEMU, supportsGuestArchitecture, OpenRISC]
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
C.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
D.
AROS Research Operating System
AROS Research Operating System is an open-source, portable reimplementation of the classic AmigaOS designed to run on modern hardware and architectures.
-
E.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: OpenRISC Target entity description: OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
C.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
D.
AROS Research Operating System
AROS Research Operating System is an open-source, portable reimplementation of the classic AmigaOS designed to run on modern hardware and architectures.
-
E.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
RISC instruction set architecture
ⓘ
open hardware project ⓘ open-source processor architecture ⓘ |
| architectureType | RISC ⓘ |
| category |
embedded microprocessors
ⓘ
instruction set architectures ⓘ open-source hardware ⓘ |
| designGoal |
flexibility
ⓘ
portability ⓘ simplicity ⓘ |
| developer | OpenCores community ⓘ |
| ecosystem |
FPGA reference designs
ⓘ
Linux kernel port ⓘ QEMU target ⓘ SoC reference platforms ⓘ newlib support ⓘ uClibc support ⓘ |
| feature |
32 general-purpose registers (in common implementations)
ⓘ
debug interface ⓘ exceptions support ⓘ interrupt support ⓘ load-store architecture ⓘ orthogonal instruction set ⓘ support for caches (in some cores) ⓘ support for hardware multiply and divide (in some cores) ⓘ |
| hasImplementation |
OR10 core
ⓘ
linked to:
OR1K
OR1200 Verilog implementation ⓘ OR1200 core ⓘ
linked to:
OR1K
OR1K architecture ⓘ
linked to:
OpenRISC
|
| hostedAt |
OpenCores.org
ⓘ
linked to:
OpenRISC
|
| influenced |
development of RISC-V ecosystem awareness
ⓘ
research on open ISAs ⓘ |
| intendedUse |
education
ⓘ
embedded systems ⓘ research ⓘ |
| license | open-source license ⓘ |
| origin | early 2000s ⓘ |
| status | actively used in research and hobbyist projects ⓘ |
| supports |
32-bit implementations
ⓘ
Harvard architecture implementations ⓘ Linux ⓘ MMU-based operating systems ⓘ uClinux ⓘ
linked to:
embedded Linux
virtual memory ⓘ |
| toolchain |
GCC
ⓘ
GDB ⓘ LLVM (partial support) ⓘ binutils ⓘ
linked to:
GNU Binutils
|
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: OpenRISC Description of subject: OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
Referenced by (4)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: OpenRISC
linked to: OpenRISC