Statements (55)
| Predicate | Object |
|---|---|
| gptkbp:instance_of |
gptkb:museum
|
| gptkbp:bfsLayer |
5
|
| gptkbp:bfsParent |
gptkb:Magma_Design_Automation
|
| gptkbp:developed_by |
gptkb:Synopsys
|
| gptkbp:first_released |
gptkb:1992
|
| gptkbp:has_feature |
Design rule checking
Signal integrity analysis Power analysis Support for system-on-chip designs Support for verification tools Design for testability Support for high-level synthesis Automated floorplanning Clock tree synthesis Design space exploration Hierarchical design support Incremental synthesis Logic optimization Multi-mode analysis Physical synthesis RTL analysis Retiming Support for ASIC flows Support for FPGA architectures Support for advanced node technologies Support for custom cells Support for design automation Support for design exploration Support for design metrics Support for design optimization Support for design reuse Support for design validation Support for low-power design Support for mixed-signal designs Support for multiple clock domains Support for standard cell libraries Technology mapping User-defined constraints |
| https://www.w3.org/2000/01/rdf-schema#label |
Design Compiler
|
| gptkbp:integrates_with |
gptkb:HSPICE
gptkb:IC_Compiler gptkb:Prime_Time |
| gptkbp:is_part_of |
Synopsys Design Suite
|
| gptkbp:is_used_by |
Chip designers
ASIC designers FPGA developers |
| gptkbp:is_used_for |
Synthesis of digital circuits
|
| gptkbp:latest_version |
2023.09
|
| gptkbp:platform |
gptkb:operating_system
|
| gptkbp:provides |
Timing analysis
Optimization features Area optimization Power optimization |
| gptkbp:supports |
VHDL
Verilog |