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gptkbp:instanceOf
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gptkb:microprocessor
|
|
gptkbp:announced
|
2014
|
|
gptkbp:architecture
|
gptkb:ARMv7-M
|
|
gptkbp:cache
|
yes
|
|
gptkbp:debugging_capability
|
yes
|
|
gptkbp:designedBy
|
gptkb:ARM_Holdings
|
|
gptkbp:family
|
gptkb:ARM_Cortex-M
|
|
gptkbp:frequency
|
up to 600 MHz
|
|
gptkbp:hasConcept
|
32-bit
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
Cortex M7
|
|
gptkbp:intendedUse
|
embedded systems
|
|
gptkbp:L1DCacheSize
|
up to 64 KB
|
|
gptkbp:L1ICacheSize
|
up to 64 KB
|
|
gptkbp:marketedAs
|
high-performance microcontroller core
|
|
gptkbp:MPU
|
yes
|
|
gptkbp:pipelineStages
|
6-stage superscalar pipeline
|
|
gptkbp:predecessor
|
gptkb:Cortex_M4
|
|
gptkbp:successor
|
gptkb:Cortex_M33
|
|
gptkbp:supports
|
gptkb:Harvard_architecture
gptkb:Thumb-2_instruction_set
hardware divide
low-latency interrupt handling
single-cycle multiply
double-precision floating point
single-precision floating point
DSP instructions
bit-banding
interrupt nesting
|
|
gptkbp:usedIn
|
gptkb:NXP_i.MX_RT_series
gptkb:STM32H7_series
Atmel SAM E70 series
|
|
gptkbp:bfsParent
|
gptkb:Cortex_M4
|
|
gptkbp:bfsLayer
|
8
|