Statements (51)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:announced |
2016
|
| gptkbp:architecture |
gptkb:ARMv8-M
|
| gptkbp:designedBy |
gptkb:Arm_Holdings
|
| gptkbp:frequency |
up to 250 MHz (implementation dependent)
|
| gptkbp:hasConcept |
32-bit
|
| gptkbp:heldBy |
gptkb:ARMv8-M_Mainline
|
| https://www.w3.org/2000/01/rdf-schema#label |
Cortex-M33
|
| gptkbp:instructionSet |
gptkb:Thumb-2
|
| gptkbp:intendedUse |
embedded systems
|
| gptkbp:marketedAs |
secure and efficient microcontroller core
|
| gptkbp:pipelineStages |
3-stage
|
| gptkbp:successor |
gptkb:Cortex-M3
gptkb:Cortex-M4 |
| gptkbp:supports |
gptkb:DWT_(Data_Watchpoint_and_Trace)
gptkb:FPB_(Flash_Patch_and_Breakpoint) gptkb:ITM_(Instrumentation_Trace_Macrocell) gptkb:TrustZone gptkb:Memory_Protection_Unit_(MPU) gptkb:Nested_Vectored_Interrupt_Controller_(NVIC) gptkb:Wake-up_Interrupt_Controller_(WIC) gptkb:ETM_(Embedded_Trace_Macrocell) co-processor interface bit manipulation instructions SIMD instructions hardware divide single-cycle multiply hardware divide (optional) atomic instructions bit-banding Digital Signal Processing (DSP) Floating Point Unit (FPU) Low-latency interrupt handling optional FPU (single-precision) barrier instructions debug and trace features event and interrupt latency reduction hardware stack pointer selection low-power sleep modes optional cache saturation arithmetic secure/non-secure states tail-chaining for interrupts unprivileged/privileged execution modes write buffer |
| gptkbp:usedIn |
gptkb:consumer_electronics
IoT devices automotive applications industrial control |
| gptkbp:bfsParent |
gptkb:microprocessor
|
| gptkbp:bfsLayer |
4
|