Triple
T737776
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | von Neumann architecture |
E14971
|
entity |
| Predicate | contrastedWith |
P278
|
FINISHED |
| Object |
Harvard architecture
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
|
E87766
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Harvard architecture | Statement: [von Neumann architecture, contrastedWith, Harvard architecture]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Harvard architecture Context triple: [von Neumann architecture, contrastedWith, Harvard architecture]
-
A.
von Neumann architecture
The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
-
B.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
C.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
SGI Altix ICE architecture
SGI Altix ICE architecture is a high-performance computing platform designed by Silicon Graphics for scalable, cluster-based supercomputers using industry-standard components and advanced interconnects.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Harvard architecture Triple: [von Neumann architecture, contrastedWith, Harvard architecture]
Generated description
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Harvard architecture Target entity description: Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
-
A.
von Neumann architecture
The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
-
B.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
C.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
SGI Altix ICE architecture
SGI Altix ICE architecture is a high-performance computing platform designed by Silicon Graphics for scalable, cluster-based supercomputers using industry-standard components and advanced interconnects.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a4934d9930819099eed80096b0597d |
completed | March 1, 2026, 7:28 p.m. |
| NER | Named-entity recognition | batch_69a4a5effc108190aea8fbe86641ba54 |
completed | March 1, 2026, 8:47 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69a64a618c248190ab1bcecba04d3da8 |
completed | March 3, 2026, 2:41 a.m. |
| NEDg | Description generation | batch_69a64b4c8bb88190aa413a4bed256129 |
completed | March 3, 2026, 2:45 a.m. |
| NED2 | Entity disambiguation (via description) | batch_69a64beaafa0819099b02cca0f6c79b7 |
completed | March 3, 2026, 2:48 a.m. |
Created at: March 1, 2026, 7:37 p.m.