Triple

T737775
Position Surface form Disambiguated ID Type / Status
Subject von Neumann architecture E14971 entity
Predicate characterizedBy P662 FINISHED
Object von Neumann bottleneck
The von Neumann bottleneck is a performance limitation in traditional computer designs where a single shared path for instructions and data between the CPU and memory creates a throughput constraint.
E14971 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: von Neumann bottleneck | Statement: [von Neumann architecture, characterizedBy, von Neumann bottleneck]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: von Neumann bottleneck
Context triple: [von Neumann architecture, characterizedBy, von Neumann bottleneck]
  • A. von Neumann architecture
    The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
  • B. Moore's law
    Moore's law is an observation and prediction that the number of transistors on an integrated circuit—and thus computing power—tends to roughly double at regular intervals, driving exponential growth in digital technology.
  • C. “Cramming more components onto integrated circuits”
    “Cramming more components onto integrated circuits” is the landmark 1965 article by Gordon E. Moore that introduced the observation later known as Moore’s Law, predicting the exponential growth of transistor density on integrated circuits.
  • D. Turing machine
    A Turing machine is an abstract computational model that manipulates symbols on an infinite tape according to a set of rules, providing a formal foundation for the concept of algorithm and computability.
  • E. Monolithic Memories
    Monolithic Memories was a semiconductor company known for developing programmable read-only memory (PROM) and logic devices after being spun off from Fairchild Semiconductor.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: von Neumann bottleneck
Triple: [von Neumann architecture, characterizedBy, von Neumann bottleneck]
Generated description
The von Neumann bottleneck is a performance limitation in traditional computer designs where a single shared path for instructions and data between the CPU and memory creates a throughput constraint.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: von Neumann bottleneck
Target entity description: The von Neumann bottleneck is a performance limitation in traditional computer designs where a single shared path for instructions and data between the CPU and memory creates a throughput constraint.
  • A. von Neumann architecture chosen
    The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
  • B. Moore's law
    Moore's law is an observation and prediction that the number of transistors on an integrated circuit—and thus computing power—tends to roughly double at regular intervals, driving exponential growth in digital technology.
  • C. “Cramming more components onto integrated circuits”
    “Cramming more components onto integrated circuits” is the landmark 1965 article by Gordon E. Moore that introduced the observation later known as Moore’s Law, predicting the exponential growth of transistor density on integrated circuits.
  • D. Turing machine
    A Turing machine is an abstract computational model that manipulates symbols on an infinite tape according to a set of rules, providing a formal foundation for the concept of algorithm and computability.
  • E. Monolithic Memories
    Monolithic Memories was a semiconductor company known for developing programmable read-only memory (PROM) and logic devices after being spun off from Fairchild Semiconductor.
  • F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a4934d9930819099eed80096b0597d completed March 1, 2026, 7:28 p.m.
NER Named-entity recognition batch_69a4a5effc108190aea8fbe86641ba54 completed March 1, 2026, 8:47 p.m.
NED1 Entity disambiguation (via context triple) batch_69a64a618c248190ab1bcecba04d3da8 completed March 3, 2026, 2:41 a.m.
NEDg Description generation batch_69a64b4c8bb88190aa413a4bed256129 completed March 3, 2026, 2:45 a.m.
NED2 Entity disambiguation (via description) batch_69a64beaafa0819099b02cca0f6c79b7 completed March 3, 2026, 2:48 a.m.
Created at: March 1, 2026, 7:37 p.m.