Triple
T38556427
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | ARM big.LITTLE heterogeneous computing |
E925257
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | heterogeneous multi-core processor architecture |
C4039
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: heterogeneous multi-core processor architecture Context triple: [ARM big.LITTLE heterogeneous computing, instanceOf, heterogeneous multi-core processor architecture]
-
A.
simultaneous multithreading technology
Simultaneous multithreading technology is a processor design technique that allows multiple independent instruction threads to be issued and executed in the same clock cycle on a single physical core, improving utilization of execution resources and overall throughput.
-
B.
SIMD instruction set extension
A SIMD instruction set extension is a set of processor instructions that enable performing the same operation simultaneously on multiple data elements to accelerate parallelizable computations.
-
C.
heterogeneous computing API specification
A heterogeneous computing API specification defines a standardized interface and behavior for coordinating and executing workloads across diverse processing units (such as CPUs, GPUs, and accelerators) within a unified programming model.
-
D.
microprocessor architecture
Microprocessor architecture is the conceptual design and organization of a computer’s central processing unit, defining its instruction set, data paths, control logic, memory hierarchy, and interfaces to efficiently execute programs.
-
E.
computer architecture
chosen
Computer architecture is the conceptual design and organization of a computer system’s fundamental components and their interactions, defining how hardware and software work together to execute instructions efficiently.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f76eaeb69c8190b367df9330d6f6af |
completed | May 3, 2026, 3:50 p.m. |
Created at: May 3, 2026, 4:32 p.m.