Triple
T3426712
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Acorn RISC Machine |
E72244
|
entity |
| Predicate | supports |
P516
|
FINISHED |
| Object |
Thumb instruction set
The Thumb instruction set is a compact 16-bit subset of the ARM architecture designed to improve code density and efficiency on ARM-based processors.
|
E356356
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Thumb instruction set | Statement: [Acorn RISC Machine, supports, Thumb instruction set]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Thumb instruction set Context triple: [Acorn RISC Machine, supports, Thumb instruction set]
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
MMIX
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
C.
POWER instruction set architecture
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Thumb instruction set Triple: [Acorn RISC Machine, supports, Thumb instruction set]
Generated description
The Thumb instruction set is a compact 16-bit subset of the ARM architecture designed to improve code density and efficiency on ARM-based processors.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Thumb instruction set Target entity description: The Thumb instruction set is a compact 16-bit subset of the ARM architecture designed to improve code density and efficiency on ARM-based processors.
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
MMIX
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
C.
POWER instruction set architecture
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ad85ae14308190bcbc25cfa0246c0b |
completed | March 8, 2026, 2:20 p.m. |
| NER | Named-entity recognition | batch_69adb982792c8190b1163eee4252210f |
completed | March 8, 2026, 6:01 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69b35478448481908e1c0f717d99f992 |
completed | March 13, 2026, 12:04 a.m. |
| NEDg | Description generation | batch_69b35546dfa0819081800009fbe8afe3 |
completed | March 13, 2026, 12:07 a.m. |
| NED2 | Entity disambiguation (via description) | batch_69b355cecc4c81908ecb5f83e89b4a00 |
completed | March 13, 2026, 12:09 a.m. |
Created at: March 8, 2026, 3:15 p.m.