Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: Xtensa | Statement: [Tensilica Xtensa LX6, architectureFamily, Xtensa]

Target entity: Xtensa
Context triple: [Tensilica Xtensa LX6, architectureFamily, Xtensa]

• A. Tensilica Xtensa LX6
  Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
• B. Nios II
  Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
• C. MIPS R5000
  The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
• D. MicroBlaze
  MicroBlaze is a soft 32-bit RISC microprocessor core designed by Xilinx for implementation on its FPGA devices.
• E. NDS32
  NDS32 is a 32-bit RISC processor architecture developed by Andes Technology, designed for embedded systems and supported by various open-source toolchains.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: Xtensa
Triple: [Tensilica Xtensa LX6, architectureFamily, Xtensa]

Xtensa is a configurable 32-bit RISC processor architecture developed by Tensilica (now part of Cadence) that allows designers to customize instructions and hardware features for embedded and SoC applications.

Target entity: Xtensa
Target entity description: Xtensa is a configurable 32-bit RISC processor architecture developed by Tensilica (now part of Cadence) that allows designers to customize instructions and hardware features for embedded and SoC applications.

• A. Tensilica Xtensa LX6 chosen
  Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
• B. Nios II
  Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
• C. MIPS R5000
  The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
• D. MicroBlaze
  MicroBlaze is a soft 32-bit RISC microprocessor core designed by Xilinx for implementation on its FPGA devices.
• E. NDS32
  NDS32 is a 32-bit RISC processor architecture developed by Andes Technology, designed for embedded systems and supported by various open-source toolchains.
• F. None of above.