Statements (23)
Predicate | Object |
---|---|
gptkbp:instanceOf |
gptkb:microprocessor
|
gptkbp:architecture |
gptkb:Xtensa
|
gptkbp:cache |
optional instruction and data cache
|
gptkbp:coreCount |
single-core
dual-core |
gptkbp:designedBy |
gptkb:Tensilica
|
https://www.w3.org/2000/01/rdf-schema#label |
Xtensa LX6
|
gptkbp:instructionSet |
gptkb:Xtensa_ISA
|
gptkbp:marketedAs |
gptkb:Cadence_Design_Systems
|
gptkbp:pipelineStages |
5-stage pipeline
|
gptkbp:releaseYear |
2016
|
gptkbp:supports |
gptkb:Harvard_architecture
hardware divide single-precision floating point hardware multiply |
gptkbp:usedIn |
gptkb:ESP32
gptkb:ESP32-D0WD gptkb:ESP32-D2WD gptkb:ESP32-S0WD gptkb:ESP32-U4WDH |
gptkbp:width |
32-bit
|
gptkbp:bfsParent |
gptkb:ESP32
|
gptkbp:bfsLayer |
5
|