Statements (31)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:canBe |
true
|
| gptkbp:category |
RISC-V implementation
Soft processor core |
| gptkbp:debugging_capability |
true
|
| gptkbp:designedBy |
gptkb:Charles_Papon
|
| gptkbp:documentation |
https://github.com/SpinalHDL/VexRiscv#documentation
|
| gptkbp:extendsTo |
RV32IM
RV32IMA RV32IMAC |
| gptkbp:firstReleased |
2018
|
| gptkbp:floatingPointUnit |
optional
|
| gptkbp:github |
https://github.com/SpinalHDL/VexRiscv
|
| gptkbp:heldBy |
gptkb:RISC-V
|
| https://www.w3.org/2000/01/rdf-schema#label |
VexRiscv
|
| gptkbp:license |
gptkb:MIT_License
|
| gptkbp:MMU |
optional
|
| gptkbp:openSource |
true
|
| gptkbp:pipelineStages |
configurable
|
| gptkbp:platform |
FPGA
ASIC |
| gptkbp:supports64bit |
true
|
| gptkbp:supportsCSR |
true
|
| gptkbp:supportsCustomExtensions |
true
|
| gptkbp:supportsInterrupts |
true
|
| gptkbp:usedIn |
gptkb:Fomu
gptkb:LiteX gptkb:OrangeCrab |
| gptkbp:writtenBy |
gptkb:SpinalHDL
|
| gptkbp:bfsParent |
gptkb:RISC-V_project
|
| gptkbp:bfsLayer |
6
|