Statements (37)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
patent
|
| gptkbp:abstract |
A method for improving efficiency in electrical circuits.
|
| gptkbp:applicationNumber |
10/780,123
|
| gptkbp:assignee |
gptkb:ABC_Corporation
|
| gptkbp:citedBy |
gptkb:US_7,123,456_B2
|
| gptkbp:claims |
20
|
| gptkbp:class |
H01L
|
| gptkbp:description |
This patent describes a novel approach to circuit design.
|
| gptkbp:drawings |
5
|
| gptkbp:examiner |
Jane_Smith
|
| gptkbp:expirationDate |
2024-02-06
|
| gptkbp:fieldOfInvention |
electrical engineering
|
| gptkbp:filingDate |
2004-02-06
|
| gptkbp:firstClaim |
A method for reducing power consumption.
A technique for minimizing electromagnetic interference. A design for a low-power operational amplifier. A device for enhancing signal integrity. A process for improving thermal management. A system for optimizing circuit layout. A method for integrating multiple functions on a single chip. |
| https://www.w3.org/2000/01/rdf-schema#label |
US 6,789,073 H11
|
| gptkbp:internationalClassification |
H01L_27/00
|
| gptkbp:inventor |
gptkb:John_Doe
|
| gptkbp:issueDate |
2004-09-14
|
| gptkbp:issuedBy |
gptkb:United_States_Patent_and_Trademark_Office
|
| gptkbp:legalStatus |
granted
|
| gptkbp:maintenanceFee |
paid
|
| gptkbp:ninthClaim |
A configuration for high-speed data transmission.
A layout for reducing parasitic capacitance. A method for enhancing reliability in manufacturing. |
| gptkbp:patentFamily |
US_6,789,073_H11_family
|
| gptkbp:patentType |
utility
|
| gptkbp:priorityDate |
2003-02-06
|
| gptkbp:relatedTo |
gptkb:US_6,500,000_B1
|
| gptkbp:status |
active
|
| gptkbp:subclass |
H01L_27/00
|
| gptkbp:technologyArea |
semiconductors
|