|
gptkbp:instanceOf
|
gptkb:microprocessor
|
|
gptkbp:acquiredBy
|
gptkb:Cadence_Design_Systems
|
|
gptkbp:architecture
|
gptkb:Xtensa
|
|
gptkbp:customs
|
true
|
|
gptkbp:developedBy
|
gptkb:Tensilica_Inc.
|
|
gptkbp:firstReleased
|
2000
|
|
gptkbp:headquarters
|
gptkb:San_Jose,_California
|
|
gptkbp:marketedAs
|
gptkb:Cadence_Design_Systems
|
|
gptkbp:notableProduct
|
gptkb:ConnX_DSP
gptkb:HiFi_DSP
Vision DSP
|
|
gptkbp:supports
|
hardware accelerators
VLIW architecture
SIMD instructions
low power operation
custom instruction set extensions
multi-core configurations
|
|
gptkbp:targetMarket
|
gptkb:consumer_electronics
gptkb:industrial_equipment
embedded systems
industrial automation
mobile devices
automotive electronics
|
|
gptkbp:usedIn
|
IoT devices
wireless communications
audio processing
image processing
automotive applications
AI acceleration
voice processing
|
|
gptkbp:website
|
https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html
|
|
gptkbp:bfsParent
|
gptkb:CDNS
|
|
gptkbp:bfsLayer
|
7
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
Tensilica DSPs
|