Statements (34)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:architecture
|
| gptkbp:aimsTo |
improve scalability
improve energy efficiency improve instruction-level parallelism |
| gptkbp:announced |
2003
|
| gptkbp:category |
computer science
microprocessor design |
| gptkbp:designedBy |
gptkb:Doug_Burger
Stephen W. Keckler |
| gptkbp:developedBy |
gptkb:University_of_Texas_at_Austin
|
| gptkbp:focusesOn |
explicit data graph execution
|
| gptkbp:fundedBy |
gptkb:National_Science_Foundation_(NSF)
gptkb:Defense_Advanced_Research_Projects_Agency_(DARPA) |
| https://www.w3.org/2000/01/rdf-schema#label |
TRIPS architecture
|
| gptkbp:influenced |
EDGE architectures
|
| gptkbp:influencedBy |
VLIW architectures
dataflow architectures |
| gptkbp:notablePublication |
The TRIPS Prototype Processor: Design, Implementation, and Evaluation, ISCA 2007
The TRIPS Computer System, IEEE Micro, 2004 |
| gptkbp:prototypeProcessor |
TRIPS prototype chip
|
| gptkbp:prototypeSpecs |
110 million transistors
130 nm process 16 execution units 366 MHz clock speed |
| gptkbp:prototypeYear |
2006
|
| gptkbp:relatedTo |
gptkb:Explicit_Data_Graph_Execution_(EDGE)
multi-core processors |
| gptkbp:standsFor |
Tera-op, Reliable, Intelligently adaptive Processing System
|
| gptkbp:type |
experimental microprocessor architecture
|
| gptkbp:uses |
block-structured ISA
dataflow execution model |
| gptkbp:bfsParent |
gptkb:Doug_Burger
gptkb:Stephen_Keckler |
| gptkbp:bfsLayer |
8
|