TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System)
GPTKB entity
Statements (23)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:announced |
2003
|
| gptkbp:architecture |
gptkb:Explicit_Data_Graph_Execution_(EDGE)
|
| gptkbp:cache |
1 MB L2 cache
32 KB L1 data cache 32 KB L1 instruction cache |
| gptkbp:coreCount |
1
|
| gptkbp:designedBy |
TRIPS research group
|
| gptkbp:developedBy |
gptkb:University_of_Texas_at_Austin
|
| gptkbp:fabricationProcess |
130 nm CMOS
|
| gptkbp:fundedBy |
gptkb:Defense_Advanced_Research_Projects_Agency_(DARPA)
|
| gptkbp:goal |
achieve high performance and energy efficiency
|
| https://www.w3.org/2000/01/rdf-schema#label |
TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System)
|
| gptkbp:instructionSet |
EDGE ISA
|
| gptkbp:manufacturer |
gptkb:IBM
|
| gptkbp:notableFor |
prototype for future scalable processors
research in post-RISC architectures |
| gptkbp:numberOfALUs |
16
|
| gptkbp:supports |
speculative execution
block-atomic execution dataflow execution |
| gptkbp:bfsParent |
gptkb:Explicit_Data_Graph_Execution_(EDGE)
|
| gptkbp:bfsLayer |
8
|