Statements (27)
Predicate | Object |
---|---|
gptkbp:instanceOf |
gptkb:microprocessor
|
gptkbp:announced |
2018
|
gptkbp:application |
embedded systems
storage controllers |
gptkbp:areaOptimized |
yes
|
gptkbp:branchPrediction |
yes
|
gptkbp:cache |
yes
|
gptkbp:developedBy |
gptkb:Western_Digital
|
gptkbp:frequency |
1.5 GHz
|
gptkbp:github |
https://github.com/chipsalliance/Cores-SweRV
|
gptkbp:hasConcept |
dual-issue
|
https://www.w3.org/2000/01/rdf-schema#label |
SweRV Core EH1
|
gptkbp:instructionSet |
gptkb:RISC-V
|
gptkbp:license |
Apache 2.0
|
gptkbp:openSource |
yes
|
gptkbp:organization |
gptkb:CHIPS_Alliance
|
gptkbp:outOfOrderExecution |
no
|
gptkbp:performanceContext |
4.9 CoreMark/MHz
|
gptkbp:pipelineStages |
9
|
gptkbp:powerOptimized |
yes
|
gptkbp:superscalar |
yes
|
gptkbp:supports |
gptkb:RV32IMC
|
gptkbp:usedIn |
gptkb:Western_Digital_storage_devices
|
gptkbp:width |
32
|
gptkbp:writtenBy |
gptkb:SystemVerilog
|
gptkbp:bfsParent |
gptkb:SweRV
|
gptkbp:bfsLayer |
7
|