Statements (22)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:architecture |
gptkb:RISC-V
|
| gptkbp:designedBy |
gptkb:Western_Digital
|
| gptkbp:firstReleased |
2019
|
| gptkbp:github |
https://github.com/chipsalliance/Cores-SweRV
|
| https://www.w3.org/2000/01/rdf-schema#label |
SweRV Core
|
| gptkbp:intendedUse |
embedded systems
|
| gptkbp:license |
gptkb:Apache_License_2.0
|
| gptkbp:notableVariant |
SweRV EH1
SweRV EH2 SweRV EL2 |
| gptkbp:openSource |
true
|
| gptkbp:partOf |
gptkb:CHIPS_Alliance
|
| gptkbp:pipelineStages |
9
|
| gptkbp:speed |
up to 1.5 GHz
|
| gptkbp:supports |
RV32IMC instruction set
|
| gptkbp:targetTechnology |
FPGA
ASIC |
| gptkbp:website |
https://github.com/chipsalliance/Cores-SweRV
|
| gptkbp:width |
32-bit
|
| gptkbp:bfsParent |
gptkb:CHIPS_Alliance
|
| gptkbp:bfsLayer |
6
|