|
gptkbp:instanceOf
|
gptkb:assembly_language
|
|
gptkbp:basedOn
|
gptkb:RISC-V_instruction_set_architecture
|
|
gptkbp:documentation
|
gptkb:RISC-V_ISA_specification
|
|
gptkbp:fileExtension
|
gptkb:RV32I
gptkb:RV64I
gptkb:C_extension
gptkb:D_extension
gptkb:M_extension
gptkb:Zifencei_extension
A extension
F extension
V extension
Zicsr extension
|
|
gptkbp:firstAppearance
|
2010s
|
|
gptkbp:hasInstruction
|
gptkb:S-type
B-type
I-type
J-type
R-type
U-type
|
|
gptkbp:hasPseudoInstructions
|
yes
|
|
gptkbp:hasSyntax
|
gptkb:AT&T_style
GNU assembler style
|
|
gptkbp:hasToolchain
|
gptkb:GCC
gptkb:LLVM
gptkb:binutils
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
RISC-V assembly
|
|
gptkbp:isDesignedBy
|
gptkb:University_of_California,_Berkeley
gptkb:RISC-V_Foundation
|
|
gptkbp:isOpenStandard
|
yes
|
|
gptkbp:registration
|
x0-x31
|
|
gptkbp:supports
|
control flow
integer arithmetic
floating point operations
logical operations
memory access
|
|
gptkbp:usedBy
|
gptkb:Alibaba_Xuantie_processors
gptkb:Microchip_PolarFire_SoC
gptkb:SiFive_processors
gptkb:Western_Digital_SweRV
|
|
gptkbp:usedFor
|
programming RISC-V processors
|
|
gptkbp:usedIn
|
education
embedded systems
research
commercial processors
|
|
gptkbp:bfsParent
|
gptkb:ARM_assembly
|
|
gptkbp:bfsLayer
|
6
|