|
gptkbp:instanceOf
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gptkb:microprocessor
|
|
gptkbp:abbreviation
|
gptkb:PA-RISC
|
|
gptkbp:addressSpace
|
48-bit virtual address space
|
|
gptkbp:cache
|
on-chip L1 cache
|
|
gptkbp:designedBy
|
gptkb:Hewlett-Packard
|
|
gptkbp:endOfDevelopment
|
2005
|
|
gptkbp:floatingPointUnit
|
optional
|
|
gptkbp:fullName
|
gptkb:Precision_Architecture_-_Reduced_Instruction_Set_Computing
|
|
gptkbp:heldBy
|
gptkb:MAX_(Multimedia_Acceleration_eXtensions)
gptkb:PA-RISC_2.0
|
|
gptkbp:instructionSet
|
gptkb:RISC
|
|
gptkbp:introducedIn
|
1986
|
|
gptkbp:marketedAs
|
gptkb:HP_Precision_Architecture
|
|
gptkbp:notableFeature
|
gptkb:PA-7100
gptkb:PA-7200
gptkb:PA-8200
gptkb:PA-8600
gptkb:PA-8000
gptkb:PA-8500
gptkb:PA-8700
gptkb:PA-7000
gptkb:PA-8800
gptkb:PA-8900
load/store architecture
simple instruction set
branch delay slots
scalable performance
backward compatibility across generations
predicated instructions
register windowing
support for both 32-bit and 64-bit computing
support for large memory configurations
support for symmetric multiprocessing
|
|
gptkbp:operatingSystem
|
gptkb:NetBSD
gptkb:OpenBSD
gptkb:Linux
gptkb:HP-UX
gptkb:MPE/iX
|
|
gptkbp:registration
|
32 general-purpose registers
|
|
gptkbp:successor
|
gptkb:Itanium_architecture
|
|
gptkbp:usedBy
|
gptkb:Hewlett-Packard
gptkb:Stratus_Technologies
gptkb:Convex_Computer
|
|
gptkbp:usedIn
|
gptkb:HP_3000_series
gptkb:HP_9000_series
|
|
gptkbp:width
|
32-bit
64-bit
|
|
gptkbp:bfsParent
|
gptkb:MPE/iX
|
|
gptkbp:bfsLayer
|
6
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
PA-RISC architecture
|