Statements (29)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:architecture |
CISC
|
| gptkbp:family |
gptkb:Motorola_68000_family
|
| gptkbp:instructionSet |
gptkb:68000_ISA
|
| gptkbp:integratedFPU |
Yes
|
| gptkbp:introducedIn |
1990
|
| gptkbp:L2Cache |
4 KB instruction, 4 KB data
|
| gptkbp:length |
32-bit
|
| gptkbp:manufacturer |
gptkb:Motorola
|
| gptkbp:MMU |
Yes
|
| gptkbp:notableFeature |
pipelined architecture
first 68000 family CPU with on-chip FPU and MMU split instruction/data cache |
| gptkbp:powerSource |
5W at 25 MHz
|
| gptkbp:predecessor |
gptkb:Motorola_68030
|
| gptkbp:speed |
33 MHz
25 MHz |
| gptkbp:successor |
gptkb:Motorola_68060
|
| gptkbp:technology |
1 µm CMOS
|
| gptkbp:transistorCount |
1.2 million
|
| gptkbp:type |
gptkb:PGA
QFP |
| gptkbp:usedIn |
gptkb:NeXT_Computer
gptkb:Apple_Macintosh_Quadra gptkb:HP_9000_Series_400 gptkb:Commodore_Amiga_4000 |
| gptkbp:bfsParent |
gptkb:HP_9000
|
| gptkbp:bfsLayer |
5
|
| https://www.w3.org/2000/01/rdf-schema#label |
Motorola 68040
|