IEEE 1500

E912828

IEEE standard testability standard

IEEE 1500 is an IEEE standard that defines a modular test architecture for embedded cores within system-on-chip (SoC) designs to facilitate efficient and standardized core-level testing.

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All labels observed (3)

Label	Occurrences
IEEE 1500 canonical	2
IEEE 1500 core test standard	1
IEEE Std 1500	1

How this entity was disambiguated

This entity first appeared as the object of triple T11226562 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: IEEE 1500
Context triple: [IEEE 1500 embedded core test standard, alsoKnownAs, IEEE 1500]

A. IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
B. IEEE 1815
IEEE 1815 is an IEEE standard that formally defines the DNP3 protocol used for reliable, secure communication in electric power and industrial control systems.
C. IEEE 1196
IEEE 1196 is the IEEE standard that formally defines the NuBus computer bus architecture used in various workstation and personal computer systems.
D. IEEE 1496-1993
IEEE 1496-1993 is an IEEE standard that specifies the SBus computer bus architecture used primarily in Sun Microsystems workstations and servers.
E. IEC 61355
IEC 61355 is an international standard that defines rules and guidelines for the structured designation and classification of documents used in industrial systems, installations, and equipment.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: IEEE 1500
Target entity description: IEEE 1500 is an IEEE standard that defines a modular test architecture for embedded cores within system-on-chip (SoC) designs to facilitate efficient and standardized core-level testing.

A. IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
B. IEEE 1815
IEEE 1815 is an IEEE standard that formally defines the DNP3 protocol used for reliable, secure communication in electric power and industrial control systems.
C. IEEE 1196
IEEE 1196 is the IEEE standard that formally defines the NuBus computer bus architecture used in various workstation and personal computer systems.
D. IEEE 1496-1993
IEEE 1496-1993 is an IEEE standard that specifies the SBus computer bus architecture used primarily in Sun Microsystems workstations and servers.
E. IEC 61355
IEC 61355 is an international standard that defines rules and guidelines for the structured designation and classification of documents used in industrial systems, installations, and equipment.
F. None of above. chosen

Statements (46)

Predicate	Object
instanceOf	IEEE standard ⓘ testability standard ⓘ
alsoKnownAs	IEEE 1500 core test standard ⓘ linked to: IEEE 1500 IEEE Std 1500 ⓘ linked to: IEEE 1500
appliesTo	embedded cores ⓘ system-on-chip (SoC) devices ⓘ
benefit	enables IP core providers to deliver standardized test interfaces ⓘ improves test reuse across different SoC integrations ⓘ reduces test development time for embedded cores ⓘ
category	electronic design automation standard ⓘ semiconductor test standard ⓘ
defines	modular test architecture for embedded cores ⓘ
documentType	technical standard ⓘ
field	design for testability ⓘ integrated circuit testing ⓘ system-on-chip design ⓘ
fullName	IEEE Standard Testability Method for Embedded Core-based Integrated Circuits ⓘ linked to: IEEE 1500 embedded core test standard
goal	enable standardized core test access ⓘ facilitate efficient core-level testing ⓘ isolate core testing from SoC-level implementation details ⓘ support reuse of core test patterns ⓘ
governs	communication between core test wrapper and SoC test access mechanism ⓘ core test wrapper behavior ⓘ
provides	standardized core test wrapper ⓘ wrapper boundary register (WBR) definition ⓘ wrapper data register (WDR) definition ⓘ wrapper instruction register (WIR) definition ⓘ wrapper serial port (WSP) definition ⓘ
publishedBy	IEEE Standards Association ⓘ Institute of Electrical and Electronics Engineers ⓘ
relatedTo	IEEE 1149.1 ⓘ linked to: IEEE 1149 family of standards IEEE 1687 ⓘ
relationship	complements IEEE 1149.1 boundary-scan at core level ⓘ
scope	digital embedded cores ⓘ
specifies	core isolation during test ⓘ core test access mechanisms ⓘ test control signals for embedded cores ⓘ
standardNumber	1500 ⓘ
supports	built-in self-test (BIST) integration at core level ⓘ hierarchical test architectures ⓘ scan-based testing of embedded cores ⓘ test pattern retargeting ⓘ
usedBy	EDA tool vendors ⓘ semiconductor companies ⓘ
usedIn	DFT (design-for-test) methodologies ⓘ SoC verification flows ⓘ

How these facts were elicited

Referenced by (4)

Full triples — surface form annotated when it differs from this entity's canonical label.

IEEE 1500 embedded core test standard → alsoKnownAs → IEEE 1500 ⓘ

Tessent → supportsStandard → IEEE 1500 ⓘ

IEEE 1500 → alsoKnownAs → IEEE Std 1500 ⓘ

linked to: IEEE 1500

IEEE 1500 → alsoKnownAs → IEEE 1500 core test standard ⓘ