MIPS III
E726418
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
All labels observed (2)
| Label | Occurrences |
|---|---|
| MIPS III canonical | 10 |
| MIPS III ISA | 3 |
How this entity was disambiguated
This entity first appeared as the object of triple T8284548 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS III Context triple: [Microprocessor without Interlocked Pipeline Stages, hasVariant, MIPS III]
-
A.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS III Target entity description: MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
A.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
- F. None of above. chosen
Statements (45)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture version
ⓘ
instruction set architecture ⓘ |
| addressSpaceSize | 64-bit virtual address space ⓘ |
| addsFeature |
64-bit general-purpose registers compared to MIPS II
ⓘ
enhanced exception handling for 64-bit mode ⓘ extended virtual address space compared to MIPS II ⓘ |
| applicationDomain |
embedded systems
ⓘ
servers ⓘ workstations ⓘ |
| architectureFamily | MIPS ⓘ |
| backwardCompatibleWith |
MIPS I
ⓘ
MIPS II ⓘ |
| bitWidth | 64-bit ⓘ |
| coprocessorModel |
CP0 system control coprocessor
ⓘ
CP1 floating-point coprocessor ⓘ |
| designedBy | MIPS Technologies ⓘ |
| endianness | bi-endian ⓘ |
| extends |
MIPS II instruction set
ⓘ
linked to:
MIPS II
|
| instructionLength | fixed 32-bit instructions ⓘ |
| instructionSetType |
RISC
ⓘ
linked to:
RISC architecture
|
| introducedFor | high-performance 64-bit systems ⓘ |
| mode |
32-bit compatibility mode
ⓘ
64-bit operation mode ⓘ |
| pipelineModel | scalar pipelined RISC ⓘ |
| predecessor | MIPS II ⓘ |
| registerWidth | 64-bit general-purpose registers ⓘ |
| standardizedAs | part of MIPS32/MIPS64 architectural lineage ⓘ |
| successor |
MIPS IV
ⓘ
MIPS64 ⓘ
linked to:
MIPS IV
|
| supports |
64-bit addressing
ⓘ
64-bit integer arithmetic ⓘ 64-bit load and store operations ⓘ atomic operations via load-linked/store-conditional ⓘ delayed branches ⓘ floating-point operations via coprocessor 1 ⓘ integer multiply and divide instructions ⓘ load delay slots (in some implementations) ⓘ memory management unit operations ⓘ virtual memory ⓘ |
| usedIn |
MIPS R4000 family
ⓘ
MIPS R4400 ⓘ
linked to:
MIPS R4000 family
MIPS R4600 ⓘ MIPS R4700 ⓘ MIPS R5000 ⓘ |
| wordSize | 32-bit word instructions ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: MIPS III Description of subject: MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
Referenced by (13)
Full triples — surface form annotated when it differs from this entity's canonical label.
subject linked to:
64-bit NEC VR4300
subject linked to:
64-bit NEC VR4300
linked to: MIPS III
linked to: MIPS III
linked to: MIPS III