Enclave Page Cache
E653457
Enclave Page Cache is a protected memory region used by Intel SGX to store and manage the code and data of secure enclaves during execution.
All labels observed (3)
| Label | Occurrences |
|---|---|
| Enclave Page Cache Map | 2 |
| Enclave Page Cache canonical | 1 |
| SGX Enclave Page Cache Map | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T7279127 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Enclave Page Cache Context triple: [Intel SGX, memoryRegion, Enclave Page Cache]
-
A.
Cache
Cache is a Symfony component that provides a flexible, high-performance caching system for optimizing application performance and reducing redundant computations or data fetching.
-
B.
WSClock page replacement algorithm
The WSClock page replacement algorithm is an operating system memory management technique that combines the working set model with a clock-based mechanism to efficiently decide which pages to evict.
-
C.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
-
D.
Address Space Layout Randomization (ASLR)
Address Space Layout Randomization (ASLR) is a security technique that randomly arranges the memory addresses used by key data areas of a process to make it harder for attackers to predict and exploit them.
-
E.
Memory Manager
Memory Manager is a classic Macintosh system software component responsible for allocating, tracking, and organizing application and system memory.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Enclave Page Cache Target entity description: Enclave Page Cache is a protected memory region used by Intel SGX to store and manage the code and data of secure enclaves during execution.
-
A.
Cache
Cache is a Symfony component that provides a flexible, high-performance caching system for optimizing application performance and reducing redundant computations or data fetching.
-
B.
WSClock page replacement algorithm
The WSClock page replacement algorithm is an operating system memory management technique that combines the working set model with a clock-based mechanism to efficiently decide which pages to evict.
-
C.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
-
D.
Address Space Layout Randomization (ASLR)
Address Space Layout Randomization (ASLR) is a security technique that randomly arranges the memory addresses used by key data areas of a process to make it harder for attackers to predict and exploit them.
-
E.
Memory Manager
Memory Manager is a classic Macintosh system software component responsible for allocating, tracking, and organizing application and system memory.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
Intel SGX component
ⓘ
protected memory region ⓘ |
| abbreviation | EPC ⓘ |
| accessControlledBy |
SGX instructions
ⓘ
hardware access checks ⓘ |
| accessRestrictedTo | enclave execution mode ⓘ |
| alsoKnownAs | EPC ⓘ |
| backedBy | processor memory encryption engine ⓘ |
| belongsToCategory |
hardware security feature
ⓘ
trusted execution environment memory ⓘ |
| capacityType | platform-dependent size ⓘ |
| contains |
enclave code pages
ⓘ
enclave data pages ⓘ enclave heap pages ⓘ enclave stack pages ⓘ enclave thread control structures ⓘ |
| definedIn |
Intel SGX architecture specifications
ⓘ
linked to:
Intel SGX
|
| encryptedIn | DRAM ⓘ |
| introducedBy |
Intel SGX version 1
ⓘ
linked to:
Intel SGX
|
| limitedResource | yes ⓘ |
| locatedIn | processor physical address space ⓘ |
| managedBy |
SGX Enclave Page Cache Map
ⓘ
linked to:
Enclave Page Cache
SGX memory management hardware ⓘ |
| monitoredBy |
Enclave Page Cache Map
ⓘ
linked to:
Enclave Page Cache
|
| pageSize | 4 KB ⓘ |
| partOf |
Intel SGX memory architecture
ⓘ
linked to:
Intel SGX
|
| purpose |
manage secure enclave memory during execution
ⓘ
store enclave code ⓘ store enclave data ⓘ |
| relatedTo |
Enclave Page Cache Map
ⓘ
linked to:
Enclave Page Cache
enclave lifecycle management ⓘ secure context switching for enclaves ⓘ |
| requires |
BIOS or firmware SGX enablement
ⓘ
SGX-capable processor ⓘ |
| securityProperty |
confidentiality protection for enclave pages
ⓘ
hardware-enforced isolation from non-enclave software ⓘ integrity protection for enclave pages ⓘ protection from direct access by system management mode ⓘ protection from direct access by the operating system ⓘ protection from direct access by virtual machine monitors ⓘ |
| supports |
dynamic page allocation for enclaves
ⓘ
page eviction to regular memory ⓘ page reloading into EPC ⓘ |
| usedBy |
Intel Software Guard Extensions
ⓘ
linked to:
Intel SGX
|
| usedFor | trusted execution environments on Intel CPUs ⓘ |
| visibleAs | reserved physical memory region ⓘ |
| vulnerabilitySurface | side-channel attacks on memory access patterns ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: Enclave Page Cache Description of subject: Enclave Page Cache is a protected memory region used by Intel SGX to store and manage the code and data of secure enclaves during execution.
Referenced by (4)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: Enclave Page Cache
linked to: Enclave Page Cache
linked to: Enclave Page Cache