|
gptkbp:instanceOf
|
gptkb:microprocessor
|
|
gptkbp:architecture
|
gptkb:ARMv6-M
|
|
gptkbp:coreMarkScore
|
0.9/MHz
|
|
gptkbp:debugging_capability
|
gptkb:Serial_Wire_Debug
|
|
gptkbp:designedBy
|
gptkb:Arm_Holdings
|
|
gptkbp:family
|
gptkb:ARM_Cortex-M
|
|
gptkbp:hasBusInterface
|
gptkb:AMBA_APB
gptkb:AMBA_AHB-Lite
|
|
gptkbp:hasInterrupts
|
yes
|
|
gptkbp:hasLinkRegister
|
yes
|
|
gptkbp:hasNestedInterrupts
|
yes
|
|
gptkbp:hasNo
|
gptkb:floating_point_unit
gptkb:Jazelle_support
gptkb:memory_management_unit
barrel shifter
SIMD instructions
branch prediction
DSP instructions
atomic instructions
bit-banding
TrustZone support
cache
divide instruction
exclusive access instructions
hardware multiply-accumulate
saturation arithmetic
trace macrocell
unaligned memory access
|
|
gptkbp:hasNVIC
|
yes
|
|
gptkbp:hasProgramCounter
|
yes
|
|
gptkbp:hasRegisterBank
|
R0-R15
|
|
gptkbp:hasStackPointer
|
yes
|
|
gptkbp:hasSysTickTimer
|
yes
|
|
gptkbp:instructionSet
|
gptkb:Thumb-1
gptkb:Thumb-2_(subset)
|
|
gptkbp:intendedUse
|
embedded systems
|
|
gptkbp:introducedIn
|
2009
|
|
gptkbp:isHarvardArchitecture
|
yes
|
|
gptkbp:isLicenseable
|
yes
|
|
gptkbp:lowPowerFeatures
|
yes
|
|
gptkbp:marketedAs
|
ultra low power
|
|
gptkbp:pipelineStages
|
3
|
|
gptkbp:speed
|
up to 50 MHz
|
|
gptkbp:successor
|
gptkb:Cortex-M0+
|
|
gptkbp:supports
|
gptkb:Thumb_instruction_set
|
|
gptkbp:usedBy
|
gptkb:Texas_Instruments
gptkb:STMicroelectronics
gptkb:Nordic_Semiconductor
gptkb:Silicon_Labs
gptkb:Analog_Devices
gptkb:Infineon
gptkb:Toshiba
gptkb:NXP
|
|
gptkbp:usedIn
|
microcontrollers
|
|
gptkbp:width
|
32-bit
|
|
gptkbp:bfsParent
|
gptkb:Cortex-M_series
gptkb:STM32
gptkb:STMicroelectronics_STM32
|
|
gptkbp:bfsLayer
|
6
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
Cortex-M0
|