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gptkbp:instanceOf
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instruction set architecture extension
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gptkbp:category
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gptkb:SIMD
gptkb:x86_instruction_set
vector instruction set
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gptkbp:compatibleWith
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gptkb:AMD_Zen_CPUs
gptkb:Apple_Silicon
gptkb:Intel_Atom
|
|
gptkbp:developedBy
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gptkb:Intel
|
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gptkbp:documentation
|
gptkb:Intel_64_and_IA-32_Architectures_Software_Developer’s_Manual
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gptkbp:extendsTo
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gptkb:SSE
gptkb:AVX
AVX2
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gptkbp:fullName
|
gptkb:Advanced_Vector_Extensions_512
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gptkbp:hasInstructionPrefix
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gptkb:EVEX
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gptkbp:hasSubgroup
|
gptkb:AVX-5124FMAPS
gptkb:AVX-5124VNNIW
gptkb:AVX-512BF16
gptkb:AVX-512BW
gptkb:AVX-512CD
gptkb:AVX-512DQ
gptkb:AVX-512ER
gptkb:AVX-512F
gptkb:AVX-512IFMA
gptkb:AVX-512PF
gptkb:AVX-512VBMI
gptkb:AVX-512VL
gptkb:AVX-512VNNI
gptkb:AVX-512VP2INTERSECT
|
|
https://www.w3.org/2000/01/rdf-schema#label
|
AVX-512
|
|
gptkbp:introducedIn
|
2016
|
|
gptkbp:maskRegisterName
|
k0-k7
|
|
gptkbp:numberOfRegisters
|
32
|
|
gptkbp:registerName
|
zmm0-zmm31
|
|
gptkbp:registerWidth
|
512 bits
|
|
gptkbp:replacedBy
|
legacy x87 FPU instructions (in some cases)
|
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gptkbp:supportedBy
|
gptkb:Intel_Ice_Lake
gptkb:Intel_Skylake-X
gptkb:Intel_Tiger_Lake
gptkb:Intel_Xeon_Phi_Knights_Landing
gptkb:Intel_Xeon_Scalable
Intel Alder Lake (partially)
Intel Core i9 (selected models)
|
|
gptkbp:supportsFloatingPointOperations
|
yes
|
|
gptkbp:supportsFusedMultiplyAdd
|
yes
|
|
gptkbp:supportsGatherScatter
|
yes
|
|
gptkbp:supportsIntegerOperations
|
yes
|
|
gptkbp:supportsMasking
|
yes
|
|
gptkbp:usedFor
|
gptkb:machine_learning
high-performance computing
scientific computing
vector processing
|
|
gptkbp:website
|
https://www.intel.com/content/www/us/en/architecture-and-technology/avx-512-overview.html
|
|
gptkbp:width
|
512
|
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gptkbp:bfsParent
|
gptkb:microprocessor
|
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gptkbp:bfsLayer
|
4
|