Triple
T986441
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | InfiniBand |
E21291
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | high-speed interconnect |
C164
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: high-speed interconnect Context triple: [InfiniBand, instanceOf, high-speed interconnect]
-
A.
serial bus interface standard
A serial bus interface standard defines the electrical, timing, and protocol rules that govern how devices communicate and exchange data over a serial communication bus.
-
B.
network connector
A network connector is a component that establishes, maintains, and manages communication links between devices or systems within a network.
-
C.
proposed high-speed ground transportation system
A proposed high-speed ground transportation system is a conceptual network of advanced vehicles, infrastructure, and control technologies designed to move passengers or freight rapidly and efficiently between destinations along dedicated terrestrial corridors.
-
D.
internet infrastructure component
An internet infrastructure component is a foundational hardware or software element—such as routers, switches, servers, cables, or protocols—that enables the transmission, routing, and reliable delivery of data across interconnected networks.
-
E.
computer hardware interface
chosen
A computer hardware interface is the physical and logical connection standard that enables communication and data exchange between a computer’s internal components or external devices and the system.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a493c383dc8190a03257f22d4b4183 |
completed | March 1, 2026, 7:30 p.m. |
Created at: March 1, 2026, 7:41 p.m.