Triple
T9783029
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Xilinx |
E237421
|
entity |
| Predicate | mainCompetitor |
P6615
|
FINISHED |
| Object | Intel (Altera) |
E29768
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Intel (Altera) | Statement: [Xilinx, mainCompetitor, Intel (Altera)]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Intel (Altera) Context triple: [Xilinx, mainCompetitor, Intel (Altera)]
-
A.
Altera
chosen
Altera is a semiconductor company best known for its programmable logic devices (FPGAs) and related design tools, now operating as a subsidiary of Intel.
-
B.
Stratix
Stratix is a high-performance family of field-programmable gate arrays (FPGAs) designed by Altera (now part of Intel) for demanding digital logic and signal processing applications.
-
C.
Lattice Semiconductor
Lattice Semiconductor is an American technology company that designs and manufactures low-power, programmable logic devices used in a wide range of electronics and embedded systems.
-
D.
Xilinx
Xilinx is a leading semiconductor company best known for its programmable logic devices, particularly FPGAs and related development tools.
-
E.
Altera HardCopy family
The Altera HardCopy family is a line of structured ASIC devices that provide a low-cost, high-performance, and power-efficient migration path from Altera FPGAs to volume production.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca84da927881909bda80caecad6010 |
completed | March 30, 2026, 2:12 p.m. |
| NER | Named-entity recognition | batch_69cda1b5714481908bf74b8bf3e4e6e8 |
completed | April 1, 2026, 10:52 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69d1c41fc5508190a759cdda8416673a |
completed | April 5, 2026, 2:08 a.m. |
Created at: March 30, 2026, 8:27 p.m.